1. Field of the Invention
The invention provides an apparatus for simulating systems that are configured in the form of networks of arrayed processing elements. For example, such apparatus may be used to verify the design of a digital logic network comprising a plurality of digital logic circuits by determining the output signals that would be developed by the network in response to the digital input signals. Other types of networks, including pipe, electric power and telephone networks, road networks and floor plans, for example, may also be simulated using apparatus constructed in accordance with this invention. Furthermore, the invention also finds utility in such fields as image processing and image analysis, in which an image can be divided into an array of picture elements, or "pixels", and the pixels analyzed in relation to their neighbors.
2. Description of the Prior Art
In the past, the logical operation of electronic networks has been verified by constructing a prototype of the network on a "breadboard", and connecting appropriate test equipment. Input signals are then applied to the inputs of the network, the output signal generated by the network is sensed, and the actual output signals are compared to the desired output signal to determine if they are identical. The process of applying the input signals and sensing the output signals must be repeated for every possible set of input signals to completely verify the circuit design. For some circuitry, for example a three-to-eight digital decoder, in which one of eight output lines is energized in response to a selected encoding of the three input lines, only eight different sets of three input signals are required to test the circuit. However, for an adder which generates sum and carry signals in response to two sixteen-bit input words, in excess of one hundred thousand possible combinations of the input signals are possible. It is apparent that verification of a breadboard prototype of such a circuit by this method would be an extremely lengthy process, if it were desired to test the circuit with all possible combinations of input signals.
The process of verifying the design of other networks can also be a lengthy task. Piping, wiring networks for electrical power and telephones, roadways and floor plans normally cannot be breadboarded, and therefore the design must be verified from the plans and testing in the field. This can be expensive if a design error must be corrected.
Furthermore, image processing and analysis, including enhancement of faint images and recognition of various shapes, can be a lengthy process if done manually. A number of computer algorithms have been written to attempt to automate the process of image recognition, but to date these have been fairly slow.